library verilog;
use verilog.vl_types.all;
entity dm is
    port(
        Data_in         : in     vl_logic_vector(31 downto 0);
        MemWr           : in     vl_logic;
        Addr            : in     vl_logic_vector(31 downto 0);
        clk             : in     vl_logic;
        rst             : in     vl_logic;
        Data_out        : out    vl_logic_vector(31 downto 0)
    );
end dm;
